1. Field of the Invention
The present invention relates to a pulse generating circuit to generate a pulse with a specified pulse width according to a one-shot pulse and to a semiconductor device provided with the same, and more particularly to the pulse generating circuit being suitably used for the pulse generation in the semiconductor devices such as an SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, or a like and to the semiconductor device provided with the above pulse generating circuit.
The present application claims priority of Japanese Patent Application No. 2002-255930 filed on Aug. 30, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 22 is a circuit diagram showing configurations of a first conventional pulse generating circuit. The first conventional pulse generating circuit is a CR (Capacitance-Resistance) type pulse generator and includes inverters 1 and 2, a resistor 3, an n-channel MOS (Metal Oxide Semiconductor) transistor 4, and a capacitor 5. The inverters 1 and 2, as shown in FIG. 22, are of a CMOS (Complementary Metal Oxide Semiconductor) structure made up of a p-channel MOS transistor 6 (see FIG. 23) and an n-channel MOS transistor 7 (see FIG. 23). The inverter 1 inverts a one-shot pulse POS with a specified pulse width fed from an outside and outputs the inverted pulse. The resistor 3 has a resistance value R1, one terminal of which is connected to an output terminal of the inverter 1 and another terminal of which is connected to a node NA. To a gate of the n-channel MOS transistor 4 is applied the one-shot pulse POS and its drain is connected to the node NA and its source is connected to a ground. The capacitor 5 has a capacitance value C1, one terminal of which is connected to the node NA and another terminal of which is connected to a ground. The inverter 2 inverts a pulse PA at the node NA and outputs the inverted pulse as an output pulse PLS. The resistor 3 and capacitor 5 make up a delay circuit having a time constant C1R1.
Next, operations of the first conventional pulse generating circuit having the configurations described above are explained by referring to a waveform diagram shown in FIG. 24. First, in an initial state, when a “L” (low) level voltage is applied to an input terminal of the inverter 1 (see FIG. 24(1)), since the inverter 1 inverts the “L” level voltage, an output voltage from the inverter 1 becomes high. Similarly, when a “L” level voltage is applied to a gate of the n-channel MOS transistor 4 (see FIG. 24 (1)), the n-channel MOS transistor 4 is in an OFF state. As a result, a voltage VA at the node NA, as shown in FIG. 24 (2), is at a “H” (high) level. This causes the inverter 2 to invert a voltage VA at the node NA, that is, a “H” level voltage and, therefore, an output voltage from the inverter 2 becomes low (see FIG. 24 (3)). At this point, the capacitor 5 accumulates electric charges corresponding to its capacitance value C1.
In such the initial state, as shown in FIG. 24 (1), when the one-shot pulse POS whose voltage changes from a “L” level to a “H” level is fed to an input terminal of the inverter 1 at time t0, since the inverter 1 inverts a change in the voltage of the one-shot pulse POS from a “L” level to a “H” level, an output voltage from the inverter 1 changes from a “H” level to a “L” level. Similarly, as shown in FIG. 24 (1), when the one-shot pulse POS whose voltage changes from a “L” level to a “H” level is fed to the gate of the n-channel MOS transistor 4 at time t0, the n-channel MOS transistor 4 changes from an OFF state to an ON state. As a result, the voltage VA at the node NA, as shown in FIG. 24 (2), changes from a “H” level to a “L” level. This causes the inverter 2 to invert the voltage VA at the node NA, that is, the change in the voltage of the one-shot pulse POS from a “H” level to a “L” level and, therefore, an output voltage from the inverter 2 changes from a “L” level to a “H” level (see FIG. 24 (3)). At this point, electrical charges accumulated in the capacitor 5 in the initial state are discharged through the n-channel MOS transistor 4.
Next, as shown in FIG. 24 (1), when a voltage of the one-shot pulse POS changes from a “H” level to a “L” Level at time t1, since the inverter 1 inverts the change in the voltage of the one-shot pulse POS from a “L” Level to a “H” level, an output voltage from the inverter 1 changes from a “L” Level to a “H” level. Similarly, as shown in FIG. 24 (1), when a voltage of the one-shot pulse POS changes from a “H” level to a “L” Level, the n-channel MOS transistor 4 changes from an ON state to an OFF state. However, since a delay circuit made up of the resistor 3 and the capacitor 5 is connected to the node NA, as shown in FIG. 24 (2), accumulation of electrical charges in the capacitor 5 starts from the time t1 and the voltage VA at the node NA comes to be boosted according to a time constant C1R1 that is determined by a capacitance value C1 of the capacitor 5 and the resistance value R1 of the resistor 3. At this point, while the voltage VA at the node NA is lower than a logical threshold value VINV of the inverter 2, an output voltage from the inverter 2 remains at a “H” level (see FIG. 24 (3)).
Then, when the voltage VA at the node NA becomes higher than the above logical threshold value VINV due to proceeding of the accumulation of electrical charges in the capacitor 5, an output voltage from the inverter 2 changes from a “H” level to a “L” Level (see FIG. 24 (3)). As described above, the first conventional pulse generating circuit, when having received the one-shot pulse POS, as shown in FIG. 24 (1), generates the output pulse PLS with a specified pulse width, as shown in FIG. 24 (3), based on operations explained above. Moreover, another conventional pulse generating circuit having configurations being similar to those of the above first conventional pulse generating circuit is disclosed in Japanese Patent Application Laid-open No. Hei 03-96112 (see FIG. 1 of the same document).
Next, FIG. 25 is a circuit diagram showing configurations of a second conventional pulse generating circuit. The second conventional pulse generating circuit is an inverter-chain-type pulse generating circuit and is made up of inverters 8 to 14, n-channel MOS transistors 15 to 17, and p-channel MOS transistors 18 to 19. Each of the inverters 8 to 14, as in the case shown in FIG. 23, is of a CMOS structure made up of a p-channel MOS transistor and an n-channel MOS transistor. Each of the inverters 8 and 9 inverts a one-shot pulse POS with a specified pulse width and outputs the inverted pulse. The inverter 10 inverts an output voltage from the inverter 9 and outputs the inverted voltage. The inverter 11 inverts an output voltage from the inverter 10 and outputs the inverted voltage. The inverter 12 inverts an output voltage from the inverter 11 and outputs the inverted voltage. Moreover, the inverter 13 inverts an output voltage from the inverter 12 and outputs the inverted voltage. The inverter 14 inverts an output voltage from the inverter 13 and outputs the inverted voltage. To a gate of the n-channel MOS transistor 15 is applied the one-shot pulse POS and its drain is connected to an output terminal of the inverter 9 and its source is connected to a ground. To a gate of the n-channel MOS transistor 16 is applied the one-shot pulse POS and its drain is connected to an output terminal of the inverter 11 and its source is connected to a ground. To a gate of the n-channel MOS transistor 17 is applied the one-shot pulse POS and its drain is connected to an output terminal of the inverter 13 and its source is connected to a ground. Moreover, a gate of the p-channel MOS transistor 18 is connected to an output terminal of the inverter 8 and a source voltage VCC is applied to its source and its drain is connected to an output terminal of the inverter 10. A gate of the p-channel MOS transistor 19 is connected to an output terminal of the inverter 8 and a source voltage VCC is applied to its source and its drain is connected to an output terminal of the inverter 12.
Next, operations of the second conventional pulse generating circuit having configurations described above are described by referring to a waveform diagram shown in FIG. 26. First, in an initial state, while a “L” Level voltage is applied to a gate of each of the n-channel MOS transistors 15 to 17 (see FIG. 26 (1)), each of the MOS transistors is in an OFF state. Likewise, while a “L” Level voltage is applied to an input terminal of the inverter 8 (see FIG. 26 (1)), since the inverter 8 inverts the “L” level voltage, an output voltage from the inverter 8 becomes high. This causes a “H” level voltage to be applied to each of the p-channel MOS transistors 18 and 19 and, therefore, each of the p-channel MOS transistors 18 and 19 is put into an OFF state. As a result, while a “L” Level voltage is applied to an input terminal of the inverter 9 (see FIG. 26 (1)), since the inverter 9 inverts the “L” level voltage, the inverter 10 inverts an output voltage from the inverter 9, the inverter 11 inverts an output voltage from the inverter 10, the inverter 12 inverts an output voltage from the inverter 11, and the inverter 13 inverts an output voltage from the inverter 12, a voltage VA at a node NA is at a “H” level, as shown in FIG. 26 (2). This causes the inverter 14 to invert the voltage VA at the node NA, that is, the “H” level voltage and, therefore, an output voltage from the inverter 14 becomes low (see FIG. 26 (3)).
In such the initial state, as shown in FIG. 26 (1), when a one-shot pulse POS whose voltage changes from a “L” Level to a “H” level is applied to each of the n-channel MOS transistors 15 to 17 at time t0, each of the n-channel MOS transistors 15 to 17 changes from an ON state to an OFF state. Similarly, as shown in FIG. 26 (1), when the one-shot pulse POS whose voltage changes from a “L” Level to a “H” level is applied to an input terminal of the inverter 8 at the time t0, since the inverter 8 inverts the change in the voltage of the one-shot pulse POS from a “L” Level to a “H” level, an output voltage from the inverter 8 changes from a “H” level to a “L” Level. This causes each of the p-channel MOS transistors 18 and 19 to change from an OFF state to an ON state. Therefore, as shown in FIG. 26 (1), when the one-shot pulse POS whose voltage changes from a “L” Level to a “H” level is applied to an input terminal of the inverter 9 at time t0, an output voltage from the inverter 9 changes from a “H” level to a “L” Level, an output voltage from the inverter 10 changes from a “H” level to a “L” Level, an output voltage from the inverter 11 changes from a “H” level to a “L” Level, an output voltage from the inverter 12 changes from a “H” level to a “L” level, and an output voltage from the inverter 13 changes from a “H” level to a “L” level, the voltage VA at the node NA, as shown in FIG. 26 (2), changes from a “H” level to a “L” Level. This causes the inverter 14 to invert the voltage VA at the node NA, that is, the change in voltage from a “H” level to a “L” level, an output voltage from the inverter 14 changes from a “L” level to a “H” level (see FIG. 26 (3)).
Next, as shown in FIG. 26 (1), when a voltage of the one-shot pulse POS changes from a “L” Level to a “H” level at time t1, each of the n-channel MOS transistors 15 to 17 change from an ON state to an OFF state. Similarly, as shown in FIG. 26 (1), when a voltage of the one-shot pulse POS changes from a “H” level to a “L” level at time t1, since the inverter 8 inverts the change in the voltage of the one-shot pulse POS from a “H” level to a “L” Level, an output voltage from the inverter 8 changes from a “L” level to a “H” level. This causes each of the p-channel MOS transistors 18 and 19 to change from an ON state to an OFF state. Therefore, as shown in FIG. 26 (1), when a voltage of the one-shot pulse POS changes from a “H” level to a “L” level at time t1, the inverter 9, according to changes in a voltage of the one-shot pulse POS from a “H” level to a “L” level, changes its output voltage from a “L” level to a “H” level during time corresponding mainly to a current driving capability of the p-channel MOS transistor making up the inverter 9.
As a result, the inverter 10, when an output voltage from the inverter 9 changes from a “L” level to a “H” level and becomes higher than a logical threshold voltage of the inverter 10, changes its output voltage from a “H” level to a “L” Level during time corresponding mainly to a current driving capability of the n-channel MOS transistor making up the inverter 10. Then, the inverter 11, when an output voltage from the inverter 10 changes from a “H” level to a “L” Level and becomes lower than a logical threshold voltage of the inverter 11, changes its output voltage from a “L” Level to a “H” level during time corresponding mainly to a current driving capability of the p-channel MOS transistor making up the inverter 11. As a result, the inverter 12, when an output voltage from the inverter 11 changes from a “L” Level toward a “H” level and becomes higher than a logical threshold voltage of the inverter 12, changes its output voltage from a “H” level to a “L” Level during time corresponding mainly to a current driving capability of the n-channel MOS transistor making up the inverter 12. Then, the inverter 13, when an output voltage from the inverter 11 changes from a “H” level to a “L” Level and becomes lower than a logical threshold voltage of the inverter 13, changes its output voltage from a “L” Level to a “H” level during time corresponding mainly to a current driving capability of the p-channel MOS transistor making up the inverter 13. Therefore, the voltage VA at the node NA, as shown in FIG. 26 (2), changes from a “L” Level to a “H” level after specified time has elapsed since the time t1. Then, the inverter 14, when the voltage VA at the node NA changes from a “L” Level toward a “H” level and becomes higher than a logical threshold voltage of the inverter 14, changes its output voltage from a “H” level to a “L” Level during time corresponding mainly to a current driving capability of the p-channel MOS transistor making up the inverter 14 (see FIG. 26 (3). As described above, the second conventional pulse generating circuit, when having received the one-shot pulse POS shown in FIG. 26 (1), generates an output pulse PLS with a specified pulse width shown in FIG. 26 (3) based on operations described above. Moreover, another conventional pulse generating circuit having configurations being similar to those of the above second conventional pulse generating circuit is disclosed in Japanese Patent Application Laid-open No. 2000-243096 (see FIG. 14 of the same document).
As explained above, in the first conventional pulse generating circuit, since the inverter 2 is placed in a back stage of the node NA, when a process parameter fluctuates at time of manufacturing semiconductor devices being equipped with the conventional pulse generating circuit, especially when a threshold value of the MOS transistor fluctuates, a logical threshold value VINV of the inverter 2 is made to be varied. This produces a disadvantage in that fluctuation occurs in a pulse width of the output pulse PLS generated by the conventional pulse generating circuit being affected adversely by changes in the logical threshold value of the MOS transistor. Reasons for that are described below.
First, the logical threshold value VINV of the inverter 2 is represented by a following equation:VINV=(VCC+Vthp+Vthn·√(βn/βp))/(1+√(βn/βp))  Equation (1)where VCC denotes a source voltage, Vthp denotes a threshold value of a p-channel MOS transistor making up the inverter 2, Vthn denotes a threshold value of an n-channel MOS transistor making up the inverter 2, βn denotes a gain constant of an n-channel MOS transistor making up the inverter 2, and βp denotes a gain constant of a p-channel MOS transistor making up the inverter 2.
Now let it be assumed that the source voltage VCC is 1.8V, the gain constantβn is equal to the gain constantβp and that ranges of variations in the threshold values Vthp and Vthn are represented by following equations (2) and (3) respectively:Vthp=−0.6±0.1 V  Equation (2)Vthn=0.6±0.1 V  Equation (3)In this case, the range of variations in the logical threshold value VINV of the inverter 2 is represented by following equations (4) to (6) by using the equation (1):VINV1=(1.8+(−0.7)+0.5·√1)/(1+√1)=0.8 V  Equation (4)VINV2=(1.8+(−0.6)+0.6·√1)/(1+√1)=0.9 V  Equation (5) VINV3=(1.8+(−0.5)+0.7·√1)/(1+√1)=1.0 V  Equation (6)where VINV1 denotes a minimum value that can be obtained when the threshold value Vthp is −0.7 V, the threshold value Vthn is 0.5 V and VINV2 denotes a typical value that can be obtained when the threshold value Vthp is −0.6 V and the threshold value Vthn is 0.6 V and VINV3 denotes a maximum value that can be obtained when the threshold value Vthp is −0.5 V and the threshold value Vthn is 0.7 V. These logical threshold values VINV1 to VINV3 are shown in FIG. 24 (2).
On the other hand, the delay circuit made up of the resistor 3 and the capacitor 5 has a primary delay characteristic and, therefore, time “t” required for the voltage VA at the node NA to reach the logical threshold value VINV of the inverter 2 from its ground level voltage at the time t1 (time point when changes start) shown in FIG. 24 (2) is given by a following equation (7):t=−C1R1·ln(1−VINV/VCC)  Equation (7)where R1 denotes a resistance value of the resistor 3, C1 denotes a capacity value of the capacitor 5, VCC denotes a source voltage, and VINV denotes a logical threshold value of the inverter 2. Here, if the resistance value R1 of the resistor 3 is 30 kΩ, the capacity value C1 of the capacitor 5 is 1 pF, that is, a time constant C1R1 is 30 nsec, and the source voltage VCC is 1.8 V, time T11 required for the voltage VA at the node NA to reach the logical threshold value VINV1 (=0.8 V), time T12 required for the voltage VA at the node NA to reach the logical threshold value VINV2 (=0.9 V), and time T13 required for the voltage VA at the node NA to reach the logical threshold value VINV3 (=1.0 V) can be represented by following equations (8) to (10) using the equation (7):T11=−30·ln(1−0.8/1.8)=17.63 nsec  Equation (8)T12=−30·ln(1−0.9/1.8)=20.79 nsec  Equation (9)T13=−30·ln(1−1.0/1.8)=24.33 nsec  Equation (10)
As is understood from FIG. 26 (3), these times T11 to T13 become pulse widths of the output pulse PLS as they are. Therefore, in the first conventional pulse generating circuit, if a logical threshold value VINV of the inverter 2 varies about 10% (0.9±0.1 V), a pulse width of the output pulse PLS varies about 17% where the pulse width is shorter and about 15% where it is longer.
Moreover, in the first conventional pulse generating circuit described above, there are some cases in which variations occurred in the resistance value R1 of the resistor 3 and/or the capacitance value C1 of the capacitor 5 are added to variations in the logical threshold value VINV of the inverter 2, which causes occurrence of large variations in the pulse width of the output pulse PLS. FIG. 27 shows times T11, T12, and T13 (see FIG. 24) required for a voltage VA at the node NA to reach each of the logical threshold values after accumulation of electric charges in the capacitor 5 has started when the source voltage VCC is 1.8 V and the time constant C1R1 of the delay circuit varies 20% (30±6 nsec) and the logical threshold value VINV of the inverter 2 varies about 10% (0.9±0.1 V). As shown in FIG. 27, in the first conventional pulse generating circuit, a pulse width of an output pulse PLS varies in a range of 14.11 nsec to 29.19 nsec (range of variations: 15.08 nsec).
On the other hand, the second conventional pulse generating circuit has a disadvantage in that, since its delay circuit is constructed using an inverter chain, if a source voltage VCC varies during operations, a current driving capability of the MOS transistor making up the inverter is changed greatly, which causes changes in a speed of an inverted output from each of the inverters and great changes in the pulse width of the output pulse PLS. Reasons for this are described below.
First, a current driving capability of an n-channel MOS transistor making up each of the inverters can be represented by following equations (11) and (12):IDSn=βn·((VGn−Vthn)2/2)  Equation (11)IDTn=βn·((VGn−Vthn)·VDn−VDn2/2)  Equation (12)
where IDSn denotes a drain current in a saturation region, IDTn denotes a drain current in a triode region (non-saturation region), βn denotes a gain constant of the n-channel MOS transistor, VGn denotes a gate voltage of the n-channel MOS transistor, Vthn denotes a threshold value of the n-channel transistor, and VDn denotes a drain voltage of the n-channel MOS transistor.
Now, let it be assumed that the threshold value Vthn of the n-channel MOS transistor is 0.6 V, the source voltage VCC is equal to the gate voltage VGn. Then, a range of variations in the source voltage VCC is given by a following equation:VCC=VG=1.8±0.2 V  Equation (13)
A range of variations in the current driving capability in the saturation region in the state as described above can be represented by following equations (14), (15), and (16):IDSn1=0.98βn  Equation (14)IDSn2=0.72βn  Equation (15)IDSn3=0.50βn  Equation (16)
where IDSn1 denotes a maximum value occurring when the source voltage VCC is 2.0 V (=VCC1), IDSn2 denotes a typical value obtained when the source voltage VCC is 1.8 V (=VCC2), and IDSn3 denotes a minimum value occurring when the source voltage VCC is 1.6 V (=VCC3). Therefore, in the second conventional pulse generating circuit, if the source voltage VCC varies about 11% (1.8±0.2 V), the current driving capability in the saturation region of the n-channel MOS transistor varies about 36% where the capability is larger and about 30% where it is smaller.
On the other hand, variations in the current driving capability in the triode region depends on a drain voltage VD. Now, let it be again assumed that VD=VCC/2, a threshold value Vthn of the n-channel MOS transistor is 0.6 V, the source voltage VCC is equal to the gate voltage VGn. Then, a range of variations in the source voltage VCC is given by the above equation (13). A range of variations in the current driving capability in the saturation region in the state as described above can be represented by following equations (17), (18), and (19):IDTn1=0.900βn  Equation (17)IDTn2=0.675βn  Equation (18)IDTn3=0.480βn  Equation (19)
where IDTn1 denotes a maximum value occurring when the source voltage VCC is 2.0 V (=VCC1), IDTn2 denotes a typical value obtained when the source voltage VCC is 1.8 V (=VCC2), and IDTn3 denotes a minimum value occurring when the source voltage VCC is 1.6 V (=VCC3). Therefore, in the second conventional pulse generating circuit, if the source voltage VCC varies about 11% (1.8±0.2 V), the current driving capability in the triode region of the n-channel MOS transistor varies about 33% where the capability is larger and about 29% where it is smaller. As a result, an average variation in the current driving capability in the saturation region and triode region of the n-channel MOS transistor is about 34.5% where the capability is larger and about 29.5% where it is smaller. The variations in the current driving capability described above occur also in a p-channel MOS transistor in the same manner as explained above.
As a result, when an inverter chain type pulse generating circuit that provides delay time of about 10 nsec is constructed of a MOS transistor having a design rule of 0.2 μm and a source voltage VCC being 1.8 V, a pulse width varies in a manner as described below. Here, it is presumed that a threshold value Vthn of the n-channel MOS transistor is 0.6 V and a threshold value Vthp of the p-channel MOS transistor is −0.6 V. That is, a pulse width T21 to be obtained when a source voltage VCC is 2.0 V (=VCC1) is about 14.2 nsec, a pulse width T22 to be obtained when the source voltage VCC is 1.8 V (=VCC2) is about 11.2 nsec, and a pulse width T23 to be obtained when the source voltage V is 1.6 V (=VCC3) is about 9.4 nsec. These pulse widths T21 to T23 are represented in FIG. 26 (3). Therefore, in the second conventional pulse generating circuit, if the source voltage VCC varies about 11% (1.8±0.2 V), a pulse width of an output pulse PLS varies about 16% where the pulse width is shorter and about 27% where it is longer, in some cases.